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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 97

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97 changes in makefile, and fifo's are now also in mod_sim_exp library JonasDC 3993d 07h /mod_sim_exp/trunk/rtl/vhdl/
95 new control logic for the core, allow for greater frequencies for the multiplier.
changes:
- autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
- mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination.
JonasDC 3994d 08h /mod_sim_exp/trunk/rtl/vhdl/
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 4007d 04h /mod_sim_exp/trunk/rtl/vhdl/
91 changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. JonasDC 4011d 12h /mod_sim_exp/trunk/rtl/vhdl/
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4013d 03h /mod_sim_exp/trunk/rtl/vhdl/
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4077d 01h /mod_sim_exp/trunk/rtl/vhdl/
86 update on previous JonasDC 4083d 02h /mod_sim_exp/trunk/rtl/vhdl/
85 changed so that reset now also affects slave register JonasDC 4083d 02h /mod_sim_exp/trunk/rtl/vhdl/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4084d 11h /mod_sim_exp/trunk/rtl/vhdl/
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4086d 12h /mod_sim_exp/trunk/rtl/vhdl/
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4103d 08h /mod_sim_exp/trunk/rtl/vhdl/
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4103d 08h /mod_sim_exp/trunk/rtl/vhdl/
77 found fault in code, now synthesizes normally JonasDC 4118d 23h /mod_sim_exp/trunk/rtl/vhdl/
75 made rw_address a vector of a fixed width JonasDC 4121d 10h /mod_sim_exp/trunk/rtl/vhdl/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4124d 06h /mod_sim_exp/trunk/rtl/vhdl/
73 updated plb interface, mem_style and device generics added JonasDC 4125d 06h /mod_sim_exp/trunk/rtl/vhdl/
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4126d 06h /mod_sim_exp/trunk/rtl/vhdl/
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4126d 09h /mod_sim_exp/trunk/rtl/vhdl/
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 4126d 09h /mod_sim_exp/trunk/rtl/vhdl/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4134d 01h /mod_sim_exp/trunk/rtl/vhdl/

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