URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 97

Rev	Log message	Author	Age	Path
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4070d 08h	/mod_sim_exp/trunk/rtl/vhdl/
62	not used anymore	JonasDC	4070d 11h	/mod_sim_exp/trunk/rtl/vhdl/
61	updated comments, added optional altera constraint	JonasDC	4070d 11h	/mod_sim_exp/trunk/rtl/vhdl/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4073d 01h	/mod_sim_exp/trunk/rtl/vhdl/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4073d 02h	/mod_sim_exp/trunk/rtl/vhdl/
55	updated resource usage in comments	JonasDC	4077d 01h	/mod_sim_exp/trunk/rtl/vhdl/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4077d 01h	/mod_sim_exp/trunk/rtl/vhdl/
53	correctly inferred ram for altera dual port ram	JonasDC	4077d 08h	/mod_sim_exp/trunk/rtl/vhdl/
52	correct inferring of blockram, no additional resources.	JonasDC	4077d 08h	/mod_sim_exp/trunk/rtl/vhdl/
51	true dual port ram for xilinx	JonasDC	4077d 09h	/mod_sim_exp/trunk/rtl/vhdl/