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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 97

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63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4134d 08h /mod_sim_exp/trunk/rtl/vhdl/
62 not used anymore JonasDC 4134d 11h /mod_sim_exp/trunk/rtl/vhdl/
61 updated comments, added optional altera constraint JonasDC 4134d 11h /mod_sim_exp/trunk/rtl/vhdl/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 4137d 01h /mod_sim_exp/trunk/rtl/vhdl/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 4137d 01h /mod_sim_exp/trunk/rtl/vhdl/
55 updated resource usage in comments JonasDC 4141d 01h /mod_sim_exp/trunk/rtl/vhdl/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4141d 01h /mod_sim_exp/trunk/rtl/vhdl/
53 correctly inferred ram for altera dual port ram JonasDC 4141d 08h /mod_sim_exp/trunk/rtl/vhdl/
52 correct inferring of blockram, no additional resources. JonasDC 4141d 08h /mod_sim_exp/trunk/rtl/vhdl/
51 true dual port ram for xilinx JonasDC 4141d 09h /mod_sim_exp/trunk/rtl/vhdl/

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