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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 21

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Rev Log message Author Age Path
21 changed x_i signal to xi JonasDC 3680d 07h /mod_sim_exp/trunk/rtl/vhdl/core/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 3680d 07h /mod_sim_exp/trunk/rtl/vhdl/core/
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 3685d 02h /mod_sim_exp/trunk/rtl/vhdl/core/
18 updated stages with comments and renamed some signals for consistency JonasDC 3686d 02h /mod_sim_exp/trunk/rtl/vhdl/core/
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 3686d 07h /mod_sim_exp/trunk/rtl/vhdl/core/
16 package with modified generic parameter for register_n JonasDC 3686d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
15 changed generic for register width from n to width for consistency JonasDC 3686d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
14 changed comments, file is now according to OC design rules JonasDC 3686d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 3686d 21h /mod_sim_exp/trunk/rtl/vhdl/core/
12 updated comments, file is now completely according to design rules JonasDC 3686d 21h /mod_sim_exp/trunk/rtl/vhdl/core/
10 changed signal input port names to correct name JonasDC 3687d 01h /mod_sim_exp/trunk/rtl/vhdl/core/
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 3687d 02h /mod_sim_exp/trunk/rtl/vhdl/core/
8 added descriptive comments JonasDC 3687d 04h /mod_sim_exp/trunk/rtl/vhdl/core/
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3687d 04h /mod_sim_exp/trunk/rtl/vhdl/core/
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3687d 04h /mod_sim_exp/trunk/rtl/vhdl/core/
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3687d 06h /mod_sim_exp/trunk/rtl/vhdl/core/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3687d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3692d 02h /mod_sim_exp/trunk/rtl/vhdl/core/

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