OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 37

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4236d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4237d 16h /mod_sim_exp/trunk/rtl/vhdl/core/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4237d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4237d 22h /mod_sim_exp/trunk/rtl/vhdl/core/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4237d 23h /mod_sim_exp/trunk/rtl/vhdl/core/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4238d 05h /mod_sim_exp/trunk/rtl/vhdl/core/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4238d 05h /mod_sim_exp/trunk/rtl/vhdl/core/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 4238d 19h /mod_sim_exp/trunk/rtl/vhdl/core/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4242d 04h /mod_sim_exp/trunk/rtl/vhdl/core/
23 added descriptive comments JonasDC 4242d 05h /mod_sim_exp/trunk/rtl/vhdl/core/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4244d 23h /mod_sim_exp/trunk/rtl/vhdl/core/
21 changed x_i signal to xi JonasDC 4246d 06h /mod_sim_exp/trunk/rtl/vhdl/core/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 4246d 06h /mod_sim_exp/trunk/rtl/vhdl/core/
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 4251d 02h /mod_sim_exp/trunk/rtl/vhdl/core/
18 updated stages with comments and renamed some signals for consistency JonasDC 4252d 01h /mod_sim_exp/trunk/rtl/vhdl/core/
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4252d 06h /mod_sim_exp/trunk/rtl/vhdl/core/
16 package with modified generic parameter for register_n JonasDC 4252d 19h /mod_sim_exp/trunk/rtl/vhdl/core/
15 changed generic for register width from n to width for consistency JonasDC 4252d 19h /mod_sim_exp/trunk/rtl/vhdl/core/
14 changed comments, file is now according to OC design rules JonasDC 4252d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 4252d 20h /mod_sim_exp/trunk/rtl/vhdl/core/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.