| Rev |
Log message |
Author |
Age |
Path |
| 38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4191d 08h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4195d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4196d 01h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4196d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4196d 08h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4196d 09h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4196d 14h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4196d 14h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4197d 04h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4200d 13h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 23 |
added descriptive comments |
JonasDC |
4200d 14h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4203d 08h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 21 |
changed x_i signal to xi |
JonasDC |
4204d 15h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4204d 16h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4209d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4210d 10h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4210d 15h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 16 |
package with modified generic parameter for register_n |
JonasDC |
4211d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 15 |
changed generic for register width from n to width for consistency |
JonasDC |
4211d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 14 |
changed comments, file is now according to OC design rules |
JonasDC |
4211d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 13 |
added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules |
JonasDC |
4211d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 12 |
updated comments, file is now completely according to design rules |
JonasDC |
4211d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 10 |
changed signal input port names to correct name |
JonasDC |
4211d 10h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 9 |
added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names |
JonasDC |
4211d 10h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 8 |
added descriptive comments |
JonasDC |
4211d 12h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 7 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4211d 13h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 6 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4211d 13h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 4 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4211d 15h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 3 |
updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation |
JonasDC |
4212d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
| 2 |
First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. |
JonasDC |
4216d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
