URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 55

Rev	Log message	Author	Age	Path
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4200d 19h	/mod_sim_exp/trunk/rtl/vhdl/core/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4201d 18h	/mod_sim_exp/trunk/rtl/vhdl/core/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4201d 23h	/mod_sim_exp/trunk/rtl/vhdl/core/
16	package with modified generic parameter for register_n	JonasDC	4202d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/
15	changed generic for register width from n to width for consistency	JonasDC	4202d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/
14	changed comments, file is now according to OC design rules	JonasDC	4202d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4202d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/
12	updated comments, file is now completely according to design rules	JonasDC	4202d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/
10	changed signal input port names to correct name	JonasDC	4202d 18h	/mod_sim_exp/trunk/rtl/vhdl/core/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4202d 18h	/mod_sim_exp/trunk/rtl/vhdl/core/