Rev |
Log message |
Author |
Age |
Path |
74 |
removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. |
JonasDC |
4158d 12h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4160d 12h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4160d 15h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4168d 07h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4168d 12h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4171d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4171d 06h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
55 |
updated resource usage in comments |
JonasDC |
4175d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4175d 06h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4255d 13h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
43 |
made the core parameters generics |
JonasDC |
4259d 07h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
41 |
removed deprecated files from version control |
JonasDC |
4265d 15h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4274d 06h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4274d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4278d 08h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4279d 05h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4279d 08h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4279d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4279d 12h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4279d 17h |
/mod_sim_exp/trunk/rtl/vhdl/core/ |