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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 81

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81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4126d 23h /mod_sim_exp/trunk/rtl/vhdl/core/
75 made rw_address a vector of a fixed width JonasDC 4145d 02h /mod_sim_exp/trunk/rtl/vhdl/core/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4147d 22h /mod_sim_exp/trunk/rtl/vhdl/core/
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4149d 21h /mod_sim_exp/trunk/rtl/vhdl/core/
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4150d 00h /mod_sim_exp/trunk/rtl/vhdl/core/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4157d 16h /mod_sim_exp/trunk/rtl/vhdl/core/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4157d 22h /mod_sim_exp/trunk/rtl/vhdl/core/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 4160d 15h /mod_sim_exp/trunk/rtl/vhdl/core/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 4160d 15h /mod_sim_exp/trunk/rtl/vhdl/core/
55 updated resource usage in comments JonasDC 4164d 15h /mod_sim_exp/trunk/rtl/vhdl/core/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4164d 15h /mod_sim_exp/trunk/rtl/vhdl/core/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4244d 23h /mod_sim_exp/trunk/rtl/vhdl/core/
43 made the core parameters generics JonasDC 4248d 16h /mod_sim_exp/trunk/rtl/vhdl/core/
41 removed deprecated files from version control JonasDC 4255d 00h /mod_sim_exp/trunk/rtl/vhdl/core/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4263d 15h /mod_sim_exp/trunk/rtl/vhdl/core/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4263d 21h /mod_sim_exp/trunk/rtl/vhdl/core/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4267d 18h /mod_sim_exp/trunk/rtl/vhdl/core/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4268d 14h /mod_sim_exp/trunk/rtl/vhdl/core/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4268d 18h /mod_sim_exp/trunk/rtl/vhdl/core/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4268d 20h /mod_sim_exp/trunk/rtl/vhdl/core/

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