URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 84

Rev	Log message	Author	Age	Path
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4197d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4197d 16h	/mod_sim_exp/trunk/rtl/vhdl/core/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4197d 17h	/mod_sim_exp/trunk/rtl/vhdl/core/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4197d 22h	/mod_sim_exp/trunk/rtl/vhdl/core/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4197d 23h	/mod_sim_exp/trunk/rtl/vhdl/core/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4198d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4201d 22h	/mod_sim_exp/trunk/rtl/vhdl/core/
23	added descriptive comments	JonasDC	4201d 23h	/mod_sim_exp/trunk/rtl/vhdl/core/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4204d 16h	/mod_sim_exp/trunk/rtl/vhdl/core/
21	changed x_i signal to xi	JonasDC	4206d 00h	/mod_sim_exp/trunk/rtl/vhdl/core/