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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 97

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Rev Log message Author Age Path
41 removed deprecated files from version control JonasDC 4186d 15h /mod_sim_exp/trunk/rtl/vhdl/core
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4195d 06h /mod_sim_exp/trunk/rtl/vhdl/core
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4195d 12h /mod_sim_exp/trunk/rtl/vhdl/core
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4199d 09h /mod_sim_exp/trunk/rtl/vhdl/core
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4200d 05h /mod_sim_exp/trunk/rtl/vhdl/core
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4200d 08h /mod_sim_exp/trunk/rtl/vhdl/core
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4200d 11h /mod_sim_exp/trunk/rtl/vhdl/core
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4200d 12h /mod_sim_exp/trunk/rtl/vhdl/core
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4200d 17h /mod_sim_exp/trunk/rtl/vhdl/core
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4200d 18h /mod_sim_exp/trunk/rtl/vhdl/core

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