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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 97

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97 changes in makefile, and fifo's are now also in mod_sim_exp library JonasDC 3984d 03h /mod_sim_exp/trunk/rtl/vhdl/core/
95 new control logic for the core, allow for greater frequencies for the multiplier.
changes:
- autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
- mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination.
JonasDC 3985d 03h /mod_sim_exp/trunk/rtl/vhdl/core/
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 3998d 00h /mod_sim_exp/trunk/rtl/vhdl/core/
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4003d 22h /mod_sim_exp/trunk/rtl/vhdl/core/
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4067d 21h /mod_sim_exp/trunk/rtl/vhdl/core/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4075d 07h /mod_sim_exp/trunk/rtl/vhdl/core/
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4077d 08h /mod_sim_exp/trunk/rtl/vhdl/core/
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4094d 04h /mod_sim_exp/trunk/rtl/vhdl/core/
75 made rw_address a vector of a fixed width JonasDC 4112d 06h /mod_sim_exp/trunk/rtl/vhdl/core/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4115d 02h /mod_sim_exp/trunk/rtl/vhdl/core/
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4117d 02h /mod_sim_exp/trunk/rtl/vhdl/core/
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4117d 05h /mod_sim_exp/trunk/rtl/vhdl/core/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4124d 21h /mod_sim_exp/trunk/rtl/vhdl/core/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4125d 02h /mod_sim_exp/trunk/rtl/vhdl/core/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 4127d 19h /mod_sim_exp/trunk/rtl/vhdl/core/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 4127d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
55 updated resource usage in comments JonasDC 4131d 19h /mod_sim_exp/trunk/rtl/vhdl/core/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4131d 19h /mod_sim_exp/trunk/rtl/vhdl/core/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4212d 03h /mod_sim_exp/trunk/rtl/vhdl/core/
43 made the core parameters generics JonasDC 4215d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
41 removed deprecated files from version control JonasDC 4222d 04h /mod_sim_exp/trunk/rtl/vhdl/core/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4230d 20h /mod_sim_exp/trunk/rtl/vhdl/core/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4231d 01h /mod_sim_exp/trunk/rtl/vhdl/core/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4234d 22h /mod_sim_exp/trunk/rtl/vhdl/core/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4235d 18h /mod_sim_exp/trunk/rtl/vhdl/core/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4235d 22h /mod_sim_exp/trunk/rtl/vhdl/core/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4236d 01h /mod_sim_exp/trunk/rtl/vhdl/core/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4236d 02h /mod_sim_exp/trunk/rtl/vhdl/core/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4236d 07h /mod_sim_exp/trunk/rtl/vhdl/core/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4236d 07h /mod_sim_exp/trunk/rtl/vhdl/core/

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