OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [adder_block.vhd] - Rev 12

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
12 updated comments, file is now completely according to design rules JonasDC 4140d 04h /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 4140d 09h /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4141d 04h /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4145d 10h /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.