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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [adder_block.vhd] - Rev 2

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2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4154d 19h /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd

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