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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [cell_1b.vhd] - Rev 14


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14 changed comments, file is now according to OC design rules JonasDC 4144d 04h /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 4144d 09h /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4145d 03h /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4149d 09h /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd

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