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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Rev 97

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97 changes in makefile, and fifo's are now also in mod_sim_exp library JonasDC 3994d 13h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 4008d 09h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4014d 08h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4078d 06h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4085d 16h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
75 made rw_address a vector of a fixed width JonasDC 4122d 16h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4125d 12h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4127d 11h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4135d 12h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4222d 13h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
43 made the core parameters generics JonasDC 4226d 06h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4241d 05h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4245d 08h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4246d 04h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4246d 08h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4246d 10h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4246d 11h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 4250d 16h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4262d 07h /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4266d 13h /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd

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