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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Rev 32

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32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4212d 12h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 4216d 16h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4228d 08h /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4232d 14h /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd

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