Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Rev 33


Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4246d 15h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4246d 16h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 4250d 20h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4262d 12h /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4266d 18h /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.