URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Rev 34

Rev	Log message	Author	Age	Path
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4549d 10h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4549d 12h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4549d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4553d 18h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4565d 09h	/mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4569d 15h	/mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd