OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Rev 36

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4244d 01h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4244d 04h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4244d 07h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4244d 08h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 4248d 13h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4260d 04h /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4264d 10h /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.