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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Rev 41

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Rev	Log message	Author	Age	Path
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4183d 00h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4187d 02h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4187d 22h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4188d 02h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4188d 05h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4188d 06h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4192d 10h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4204d 02h	/mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4208d 08h	/mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd

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