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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_core.vhd] - Rev 84

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84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 3411d 01h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
75 made rw_address a vector of a fixed width JonasDC 3448d 00h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 3450d 21h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 3452d 20h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 3460d 21h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3547d 21h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
43 made the core parameters generics JonasDC 3551d 15h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 3566d 14h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 3570d 17h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 3571d 13h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 3571d 16h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 3571d 19h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 3571d 20h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 3576d 01h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3587d 16h /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3591d 22h /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd

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