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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Rev 32

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Rev	Log message	Author	Age	Path
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4202d 10h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4202d 11h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4203d 01h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4206d 10h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
23	added descriptive comments	JonasDC	4206d 11h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4209d 04h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
21	changed x_i signal to xi	JonasDC	4210d 12h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4210d 12h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4215d 07h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
18	updated stages with comments and renamed some signals for consistency	JonasDC	4216d 07h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4216d 12h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
16	package with modified generic parameter for register_n	JonasDC	4217d 01h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4217d 07h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4218d 01h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd

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