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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Rev 34

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Rev	Log message	Author	Age	Path
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4581d 02h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4581d 11h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4581d 12h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4582d 02h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4585d 11h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
23	added descriptive comments	JonasDC	4585d 12h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4588d 05h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
21	changed x_i signal to xi	JonasDC	4589d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4589d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4594d 08h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
18	updated stages with comments and renamed some signals for consistency	JonasDC	4595d 08h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4595d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
16	package with modified generic parameter for register_n	JonasDC	4596d 02h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4596d 08h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4597d 02h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd

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