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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Rev 69

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69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4040d 06h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4048d 01h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4048d 06h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4135d 07h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
43 made the core parameters generics JonasDC 4139d 00h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
41 removed deprecated files from version control JonasDC 4145d 08h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4154d 00h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4158d 02h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4159d 02h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4159d 11h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4159d 11h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 4160d 01h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 4163d 10h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
23 added descriptive comments JonasDC 4163d 11h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4166d 05h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
21 changed x_i signal to xi JonasDC 4167d 12h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 4167d 13h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 4172d 08h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
18 updated stages with comments and renamed some signals for consistency JonasDC 4173d 07h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4173d 12h /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd

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