| Rev |
Log message |
Author |
Age |
Path |
| 75 |
made rw_address a vector of a fixed width |
JonasDC |
4063d 21h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4068d 17h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4076d 12h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4076d 18h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4163d 18h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 43 |
made the core parameters generics |
JonasDC |
4167d 12h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 41 |
removed deprecated files from version control |
JonasDC |
4173d 20h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4182d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4186d 14h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4187d 13h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4187d 22h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4187d 23h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4188d 13h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4191d 22h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 23 |
added descriptive comments |
JonasDC |
4191d 23h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4194d 16h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 21 |
changed x_i signal to xi |
JonasDC |
4196d 00h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4196d 00h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4200d 19h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
| 18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4201d 19h |
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd |
