URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [modulus_ram_asym.vhd] - Rev 89

Rev	Log message	Author	Age	Path
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4019d 19h	/mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4029d 06h	/mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4046d 02h	/mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4069d 03h	/mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd