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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [modulus_ram_gen.vhd] - Rev 94

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94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 4171d 18h /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4177d 17h /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4241d 15h /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4298d 21h /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd

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