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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mont_ctrl.vhd] - Rev 39


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39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4181d 06h /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 4190d 17h /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4202d 08h /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4206d 14h /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd

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