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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mont_ctrl.vhd] - Rev 95

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95 new control logic for the core, allow for greater frequencies for the multiplier.
changes:
- autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
- mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination.
JonasDC 3960d 19h /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4206d 11h /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 4215d 22h /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4227d 14h /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4231d 19h /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd

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