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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [register_1b.vhd] - Rev 6

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6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3698d 08h /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3699d 00h /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3703d 06h /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd

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