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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [x_shift_reg.vhd] - Rev 21

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Rev Log message Author Age Path
21 changed x_i signal to xi JonasDC 3689d 15h /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 3689d 16h /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3697d 05h /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3701d 10h /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd

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