| Rev |
Log message |
Author |
Age |
Path |
| 63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4090d 18h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4093d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4093d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 55 |
updated resource usage in comments |
JonasDC |
4097d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4097d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4177d 19h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 43 |
made the core parameters generics |
JonasDC |
4181d 12h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 41 |
removed deprecated files from version control |
JonasDC |
4187d 20h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4196d 11h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4196d 17h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4200d 14h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4201d 10h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4201d 14h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4201d 17h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4201d 18h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4201d 23h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4201d 23h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4202d 13h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4205d 22h |
/mod_sim_exp/trunk/rtl/vhdl/core |
| 23 |
added descriptive comments |
JonasDC |
4205d 23h |
/mod_sim_exp/trunk/rtl/vhdl/core |
