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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] - Rev 94

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Rev Log message Author Age Path
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 3944d 02h /mod_sim_exp/trunk/rtl/vhdl/interface/
91 changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. JonasDC 3948d 10h /mod_sim_exp/trunk/rtl/vhdl/interface/
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3950d 00h /mod_sim_exp/trunk/rtl/vhdl/interface/
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4013d 23h /mod_sim_exp/trunk/rtl/vhdl/interface/
86 update on previous JonasDC 4020d 00h /mod_sim_exp/trunk/rtl/vhdl/interface/
85 changed so that reset now also affects slave register JonasDC 4020d 00h /mod_sim_exp/trunk/rtl/vhdl/interface/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4021d 09h /mod_sim_exp/trunk/rtl/vhdl/interface/
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4040d 06h /mod_sim_exp/trunk/rtl/vhdl/interface/
77 found fault in code, now synthesizes normally JonasDC 4055d 21h /mod_sim_exp/trunk/rtl/vhdl/interface/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4061d 04h /mod_sim_exp/trunk/rtl/vhdl/interface/
73 updated plb interface, mem_style and device generics added JonasDC 4062d 03h /mod_sim_exp/trunk/rtl/vhdl/interface/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4070d 23h /mod_sim_exp/trunk/rtl/vhdl/interface/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4158d 05h /mod_sim_exp/trunk/rtl/vhdl/interface/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4161d 23h /mod_sim_exp/trunk/rtl/vhdl/interface/
43 made the core parameters generics JonasDC 4161d 23h /mod_sim_exp/trunk/rtl/vhdl/interface/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4168d 06h /mod_sim_exp/trunk/rtl/vhdl/interface/
40 adjusted core instantiation to new core module name JonasDC 4176d 10h /mod_sim_exp/trunk/rtl/vhdl/interface/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4202d 06h /mod_sim_exp/trunk/rtl/vhdl/interface/

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