URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] - Rev 41

Rev	Log message	Author	Age	Path
40	adjusted core instantiation to new core module name	JonasDC	4196d 16h	/mod_sim_exp/trunk/rtl/vhdl/interface/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4222d 12h	/mod_sim_exp/trunk/rtl/vhdl/interface/