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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] - Rev 44


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Rev Log message Author Age Path
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4223d 11h /mod_sim_exp/trunk/rtl/vhdl/interface/
43 made the core parameters generics JonasDC 4223d 12h /mod_sim_exp/trunk/rtl/vhdl/interface/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4229d 19h /mod_sim_exp/trunk/rtl/vhdl/interface/
40 adjusted core instantiation to new core module name JonasDC 4237d 23h /mod_sim_exp/trunk/rtl/vhdl/interface/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4263d 19h /mod_sim_exp/trunk/rtl/vhdl/interface/

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