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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] - Rev 45

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Rev Log message Author Age Path
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4192d 05h /mod_sim_exp/trunk/rtl/vhdl/interface/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4195d 23h /mod_sim_exp/trunk/rtl/vhdl/interface/
43 made the core parameters generics JonasDC 4195d 23h /mod_sim_exp/trunk/rtl/vhdl/interface/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4202d 07h /mod_sim_exp/trunk/rtl/vhdl/interface/
40 adjusted core instantiation to new core module name JonasDC 4210d 11h /mod_sim_exp/trunk/rtl/vhdl/interface/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4236d 06h /mod_sim_exp/trunk/rtl/vhdl/interface/

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