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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] - Rev 66

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Rev Log message Author Age Path
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4108d 21h /mod_sim_exp/trunk/rtl/vhdl/interface/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4196d 03h /mod_sim_exp/trunk/rtl/vhdl/interface/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4199d 20h /mod_sim_exp/trunk/rtl/vhdl/interface/
43 made the core parameters generics JonasDC 4199d 20h /mod_sim_exp/trunk/rtl/vhdl/interface/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4206d 04h /mod_sim_exp/trunk/rtl/vhdl/interface/
40 adjusted core instantiation to new core module name JonasDC 4214d 08h /mod_sim_exp/trunk/rtl/vhdl/interface/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4240d 04h /mod_sim_exp/trunk/rtl/vhdl/interface/

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