Rev |
Log message |
Author |
Age |
Path |
94 |
BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx |
JonasDC |
3949d 09h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
91 |
changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. |
JonasDC |
3953d 18h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
90 |
reverted changes from previous revision, updated AXI version with testbench |
JonasDC |
3955d 08h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
89 |
updated vhdl files so now different clock frequencies are posible for the core and bus interface. |
JonasDC |
4019d 06h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
86 |
update on previous |
JonasDC |
4025d 08h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
85 |
changed so that reset now also affects slave register |
JonasDC |
4025d 08h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
84 |
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS |
JonasDC |
4026d 17h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
82 |
added first version of axi-lite interface and testbench for basic axi-lite operations, now under test |
JonasDC |
4045d 13h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
77 |
found fault in code, now synthesizes normally |
JonasDC |
4061d 05h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
74 |
removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. |
JonasDC |
4066d 12h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
73 |
updated plb interface, mem_style and device generics added |
JonasDC |
4067d 11h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4076d 06h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4163d 13h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4167d 06h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
43 |
made the core parameters generics |
JonasDC |
4167d 06h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4173d 14h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4181d 18h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |
2 |
First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. |
JonasDC |
4207d 14h |
/mod_sim_exp/trunk/rtl/vhdl/interface/ |