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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [axi] - Rev 94

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Rev	Log message	Author	Age	Path
94	BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include: - changed RAM and memory to support different clocks - new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org) - parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers) - added logic for control signals to cross from one clock domain to another - updated testbenches and interfaces accordingly - added log of synthesis of the 2 new fifo's for Xilinx	JonasDC	3972d 02h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi
91	changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register.	JonasDC	3976d 10h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	3978d 01h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4041d 23h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi
86	update on previous	JonasDC	4048d 00h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi
85	changed so that reset now also affects slave register	JonasDC	4048d 00h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4049d 09h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4068d 06h	/mod_sim_exp/trunk/rtl/vhdl/interface/axi

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