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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] - Rev 65

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Rev Log message Author Age Path
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4075d 18h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4163d 00h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4166d 17h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
43 made the core parameters generics JonasDC 4166d 17h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4173d 01h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
40 adjusted core instantiation to new core module name JonasDC 4181d 05h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4207d 01h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/

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