URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] - Rev 66

Rev	Log message	Author	Age	Path
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4083d 08h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4170d 14h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4174d 07h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/
43	made the core parameters generics	JonasDC	4174d 07h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4180d 15h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/
40	adjusted core instantiation to new core module name	JonasDC	4188d 19h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4214d 15h	/mod_sim_exp/trunk/rtl/vhdl/interface/plb/