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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Rev 40

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40 adjusted core instantiation to new core module name JonasDC 3666d 23h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3692d 18h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd

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