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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Rev 65

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Rev Log message Author Age Path
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 3567d 01h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3654d 07h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
43 made the core parameters generics JonasDC 3658d 01h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3664d 09h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
40 adjusted core instantiation to new core module name JonasDC 3672d 13h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3698d 08h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd

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