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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Rev 65

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Rev Log message Author Age Path
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4070d 13h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4157d 19h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
43 made the core parameters generics JonasDC 4161d 13h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4167d 20h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
40 adjusted core instantiation to new core module name JonasDC 4176d 00h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4201d 20h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd

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