OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Rev 73

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 updated plb interface, mem_style and device generics added JonasDC 4093d 12h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4102d 08h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4189d 14h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
43 made the core parameters generics JonasDC 4193d 07h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4199d 15h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
40 adjusted core instantiation to new core module name JonasDC 4207d 19h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4233d 15h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.