OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] [user_logic.vhd] - Rev 94

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 3370d 20h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 3448d 04h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
77 found fault in code, now synthesizes normally JonasDC 3482d 16h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 3487d 23h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
73 updated plb interface, mem_style and device generics added JonasDC 3488d 22h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 3497d 17h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3585d 00h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
43 made the core parameters generics JonasDC 3588d 17h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3595d 01h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
40 adjusted core instantiation to new core module name JonasDC 3603d 05h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3629d 00h /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.