URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] - Rev 89

Rev	Log message	Author	Age	Path
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4166d 01h	/mod_sim_exp/trunk/rtl/vhdl/ram/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4175d 12h	/mod_sim_exp/trunk/rtl/vhdl/ram/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4215d 09h	/mod_sim_exp/trunk/rtl/vhdl/ram/
62	not used anymore	JonasDC	4223d 09h	/mod_sim_exp/trunk/rtl/vhdl/ram/
61	updated comments, added optional altera constraint	JonasDC	4223d 09h	/mod_sim_exp/trunk/rtl/vhdl/ram/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4225d 23h	/mod_sim_exp/trunk/rtl/vhdl/ram/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4226d 00h	/mod_sim_exp/trunk/rtl/vhdl/ram/
53	correctly inferred ram for altera dual port ram	JonasDC	4230d 06h	/mod_sim_exp/trunk/rtl/vhdl/ram/
52	correct inferring of blockram, no additional resources.	JonasDC	4230d 06h	/mod_sim_exp/trunk/rtl/vhdl/ram/
51	true dual port ram for xilinx	JonasDC	4230d 07h	/mod_sim_exp/trunk/rtl/vhdl/ram/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4230d 07h	/mod_sim_exp/trunk/rtl/vhdl/ram/