URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [ram/] [dpram_generic.vhd] - Rev 89

Rev	Log message	Author	Age	Path
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4024d 09h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd
61	updated comments, added optional altera constraint	JonasDC	4081d 17h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4084d 07h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4084d 08h	/mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd