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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [sim/] - Rev 32

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31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4187d 00h /mod_sim_exp/trunk/sim/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4187d 01h /mod_sim_exp/trunk/sim/
28 updated makefile for new pipeline sources JonasDC 4187d 15h /mod_sim_exp/trunk/sim/
27 test input values for multiplier_tb JonasDC 4187d 15h /mod_sim_exp/trunk/sim/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4191d 00h /mod_sim_exp/trunk/sim/
11 simulation output folder JonasDC 4201d 18h /mod_sim_exp/trunk/sim/
5 not needed on svn, is generated by testbench JonasDC 4202d 00h /mod_sim_exp/trunk/sim/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4202d 15h /mod_sim_exp/trunk/sim/

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