OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [sim/] - Rev 87

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 3457d 16h /mod_sim_exp/trunk/sim/
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 3499d 11h /mod_sim_exp/trunk/sim/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 3507d 06h /mod_sim_exp/trunk/sim/
41 removed deprecated files from version control JonasDC 3604d 13h /mod_sim_exp/trunk/sim/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 3618d 06h /mod_sim_exp/trunk/sim/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 3618d 16h /mod_sim_exp/trunk/sim/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 3618d 16h /mod_sim_exp/trunk/sim/
28 updated makefile for new pipeline sources JonasDC 3619d 06h /mod_sim_exp/trunk/sim/
27 test input values for multiplier_tb JonasDC 3619d 06h /mod_sim_exp/trunk/sim/
24 changed names of top-level module to mod_sim_exp_core JonasDC 3622d 15h /mod_sim_exp/trunk/sim/
11 simulation output folder JonasDC 3633d 10h /mod_sim_exp/trunk/sim/
5 not needed on svn, is generated by testbench JonasDC 3633d 15h /mod_sim_exp/trunk/sim/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3634d 07h /mod_sim_exp/trunk/sim/

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.