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[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Rev 31

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31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 3683d 06h /mod_sim_exp/trunk/sim/Makefile
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 3683d 06h /mod_sim_exp/trunk/sim/Makefile
28 updated makefile for new pipeline sources JonasDC 3683d 20h /mod_sim_exp/trunk/sim/Makefile
24 changed names of top-level module to mod_sim_exp_core JonasDC 3687d 05h /mod_sim_exp/trunk/sim/Makefile
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3698d 21h /mod_sim_exp/trunk/sim/Makefile

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