URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [sim/] [Makefile] - Rev 31

Rev	Log message	Author	Age	Path
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4180d 06h	/mod_sim_exp/trunk/sim/Makefile
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4180d 06h	/mod_sim_exp/trunk/sim/Makefile
28	updated makefile for new pipeline sources	JonasDC	4180d 20h	/mod_sim_exp/trunk/sim/Makefile
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4184d 05h	/mod_sim_exp/trunk/sim/Makefile
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4195d 21h	/mod_sim_exp/trunk/sim/Makefile